The present invention relates to a semiconductor chip package configuration and method of formation and more particularly to such a chip package configuration and method of formation for facilitating attaching and testing of the chip package and subsequent surface mounting thereof on a substrate such as a printed circuit board or the like. By chip package, it is meant the combination of a semiconductor chip and surrounding enclosure with protruding leads.
Numerous techniques have been disclosed in the prior art for forming semiconductor chip packages and mounting them on substrates such as printed circuit boards to facilitate subsequent operation. Conventionally, the individual semiconductor chip packages have been electrically tested in test devices having sockets or tests heads arranged for electrical communication with the respective leads on the chip pakcage. Such testing makes it necessary, of course, to maintain the leads in electrical isolation from each other. Thereafter, the chip packages are mounted either manually or automatically upon a suitable substrate such as a printed circuit board with the individual leads being interconnected with respective conductors on the substrate. The leads and conductors are then joined together using techniques which are well known in the prior art, such as vapor phase soldering, thermode reflow soldering, etc.
As can be seen, alignment of the leads on the chip package is of critical importance both during testing and mounting. As noted above, the leads must be maintained in electrical isolation from each other during testing. Spacing is equally critical during mounting of the chip package on a substrate in order to assure proper alignment and attachment of the respective leads to conductors on the substrate.
In a conventional technique for forming the basic components of a semiconductor chip package such as referred to above, the leads are formed in a lead frame comprising dam bars and/or tie bars which maintain proper spacing between the leads, facilitate application of the packaging to the chip package, etc. The tie bars connect adjacent leads at their outermost perimeter, while dam bars connect adjacent leads at the innermost point of the leads next to the semiconductor chip package package. However, with the tie bars and dam bars being formed from conductive material along with other portions of the lead frame, they must be removed or disconnected from between the leads before testing of the chip package can begin in order to establish electrical isolation for the leads. Particularly in more recently developed techniques of surface mounting, as contemplated by the present invention, each of the leads project from the semiconductor package in cantilevered fashion so that they are susceptible to dislocation which may result in undesirable contact between adjacent leads or improper registration and, hencemounting of the leads on the substrate.
This problem has been found to be even more severe recently, because of the reduced pitch or spacing of the leads necessitated by the existence of much higher density integrated circuit chip packages having high pin or lead count. For example, in typical semiconductor chip packages of the type employed at the present time, the pitch or spacing of the leads has commonly been reduced from about 0.050 to 0.025 inches in order to permit greater lead density in the chip packages.
With the contemplation of ever greater lead densities for such semiconductor chip packages, there is an increasing need for means to maintain proper alignment and spacing of the leads during both testing and mounting of the chip packages on suitable substrates.